For years and years in the computer industry there was only one type of dynamic RAM used, the Page Mode RAM and later the Fast Page Mode RAM. Now, since the advance in CPU performance increases as quick, these old RAM types are one of the things that keep computers slower than necessary. The first thing to get around the slowness of the main memory was the introduction of caches in the CPUs and on the motherboards, but now even that isn't enough anymore and so new RAM types have to be developed and used, if the main memory wants to keep up with the speed of the CPU rather than slowing it down.
If you should be interested in more information about DRAM, particularly the outlook into the nearer future and a comparison between the two new technologies BEDO RAM and SDRAM, you shouldn't miss Synchronous DRAMs: The DRAM of the Future by IBM. Another interesting
page regarding DRAM is from Micron.
Since the new SDRAMs came out, the good old DIMM standard is getting popular in PC systems and the poor PC users don't know what it is. I know that all Mac users will smile now - MACs have been using DIMMs for ages. So what is it ?
DIMM stands for Dual In line Memory Module in opposition to SIMM, which simply is Single In
line Memory Module. DIMM or SIMM only specifies the package RAM comes in, not the type!
You can get each RAM type for each module, but as far as PCs are concerned, DIMMs are at
present only used for SDRAM. The benefit of a DIMM is that it has a 64 bit (72 bit with parity)
wide data path and therefore can be used single in Pentium boards, which normally require two
SIMMs to work (valid for the fast chipsets only, SiS and others got around that by decreasing
memory performance). You also can mix each size with another - no thinking in pairs anymore as
for SIMMs. Well that's all the secret about DIMMs.
Well, that's the oldie and least sophisticated among all these RAM types. It nowadays comes in two different flavors, 70ns and 60ns access time. The 60 ns one you'll need if you have a Pentium with a bus speed of 66 MHz (in 100,133,166 and 200 MHz Pentiums).Well, I think you know this kind of RAM, it's also used dafaultly on video cards, called just DRAM and sometimes with an access time of only 48 ns there. Actually VRAM or Video RAM is nothing much different, it only is so called dual ported, which means it can be accessed by the RAMDAC independently of the CPU accesses via the second port, so that the RAMDAC doesn't have to wait for the CPU access to finish and vice versa - this makes it quite a bit faster than DRAM.
The Fast PageMode means, that the RAM logic 'hopes', that the next access will be in the same row, saving time if this should be the case.
The fastest access speed of FPM RAM in CPU cycles is 5-3-3-3 for a four data
(Byte/Word/Dword) burst read.
A series of FPM read access's starts with the activation of a row in the DRAM array by providing a row address and bringing RAS LOW. Then, multiple column access's may be executed by cycling CAS. Each CAS cycle includes applying a column address, bringing CAS LOW, waiting for valid data-out, latching data in the system and bringing CAS HIGH to prepare for the next cycle, in that order. This sequence of events is shown in the Figure. Note that CAS going HIGH disables the data outputs, and therefore must occur only after the valid data is latched by the system.
The Extended Data Output RAM (EDO RAM)
A set of gates latches the output value till read by the CPU, which is important for fast CPUs like Pentiums, it handles better quick sequential reads than FPM RAM. It is a variation of the regular FPM RAM with minor change in the CAS# and data output timing. Data comes out of EDO DRAM more frequently than from standard DRAM. The CAS# timing can be condensed to crank more data out in a given period of time. In the Triton chip set, the difference is X-2-2-2 vs. X-3-3-3 in terms of CPU clocks.
It comes in three speeds 70ns, 60ns and 50ns, where 60ns you need at least if using 66 MHz bus speed and if you should use the new Triton HX or VX chipset you also can take advantage of 50ns EDO - so if you should get EDO, never get 70ns or you'll never be able to upgrade to a P100/133/166/200, get 60ns or if your not too greedy get 50ns in the first place !
The problem with EDO RAM when looking in the future is that it hardly works with any bus speed higher than 66 MHz, which is already reached. As CPUs demand higher bus speeds and the Cyrix 6x86 already needing 75 MHz, the death of the EDO RAM seems already to be visible on the horizon.
The fastest access speed of EDO RAM in CPU cycles is 5-2-2-2 for a four data
(Byte/Word/Dword) burst read.
What is EDO RAM?
EDO (Extended Data Output) is the newest DRAM chip technology in a series of innovations
which include "nibble mode", "write per bit" and "fast page mode". EDO is a bit better than "fast
page mode": for a given speed on the chip (for instance 70ns, 60ns) the EDO chip processor
allows a 10 - 15 % faster access to the memory than with an "fast mode chip". But the computer
system must be ready to use the extra efficiency the EDO can offer. Pentium machines which uses
Intel's Triton chipset are designed to use EDO RAM. If you put an EDO RAM chip into a
machine that doesn't recognize EDO, the system will still work, but you will not get increased
performance.
Why is EDO RAM faster?
AA DRAM chip is made as a matrix of bits where each bit has a row address and a column
address. The memory manager must tell the chip the row and column address to be able to
get those data each bit contains. A 70ns chip must produce a bit with data within 70ns. In
addition to the 70ns it takes to get information from the chip, it takes extra time to get the
same information to the processor and to prepare for the receipt of the next instructions. A
complete memory access cycle, from the moment the memory manager delivers an address
to the memory chip, until the memory manager is ready to deliver the next address to the
chip, can vary between 85 to 125ns. Each improvement in the chip technology make the
process a bit more effective. For instance, the "fast page" technology was a innovation
which made it quicker to access data in the same row. If a bit was in the same row as the
previous, the memory manager wouldn't have to repeat the row address instructions, it just
had to deliver the next column address. The efficiency and speed of the delivering of data
was improved for all the data on the same page. EDO RAM is a innovation when it comes
to memory. It makes the memory manager able to save even more time by decreasing the
waiting time that is normally needed to deliver the next column address, by 10 ns. The
processor is getting the information more rapidly and through that the performance of the
machine is increased with 10 to 15%.
What does the memory look like?
A EDO RAM module look quite like a standard non-parity memory chip. The only
difference is the difference of the chip type on the motherboard.
Extended Data-Out page mode read access's are similar to those of FPM, with the exception that CAS going HIGH does not disable the data outputs, and the data latch is used to guarantee that valid data is held until CAS goes LOW again. In the case of EDO, the data latch (which is already available) is now controlled during page-mode access's by CAS. Data is effectively captured in the latch as a result of CAS going HIGH. A new address can then be applied, and new data accessed in the array, without corrupting the output data from the previous access.
TheBEDO RAM, as the name already says, reads data in a burst, which means that after the address has been provided, the next three data are read in only one clock cycle each, the CPU is able to read data in a 5-1-1-1 burst. This RAM type is at present only supported by the VIA chipsets 580VP, 590VP, 680VP. The main downside of the really fast BEDO RAM seems also to be the incapability to coupe with bus speeds faster than 66 MHz.
BEDO read access's differ from those of EDO in two ways. First, because the data latch is replaced by a register (i.e. an additional latch stage is added) data will not reach the outputs as a result of the first CAS cycle. The benefit of this internal pipeline stage is that data will appear in a shorter time from the activating CAS edge in the second cycle (i.e. tCAC is shorter). The second difference is that BEDO devices include an internal address counter so that only the initial address in a burst of four needs to be provided externally. The simplified functional representation for BEDO and the sequence of events is shown in the Figure. The three Figures illustrate how tPC is progressively reduced when moving from FPM to EDO to BEDO, and also that tCAC is reduced and tCPA eliminated when using BEDO DRAMs. It can also be seen in the Figure that the first CAS cycle for BEDO, which loads the internal pipeline, does not cause additional delay in receiving the first data element. This is because access to the first data element is limited by tRAC (the access time from RAS) which in effect hides the first CAS cycle. Here the link to the Micron BEDOInformation Page, for people who want to get real in-depth information.
The Synchronous Dynamic RAM (SDRAM) - THE WINNER
Well, here we are, this is the othertype of RAM, which possibly will get very popular soon, 'cause it's supported by the new Intel Triton VX chipset and all new VIA chipsets, the 580VP, 590VP (for Pentiums, 6x86) and the 680VP (for Pentium Pro)! As the name says already, this RAM is able to handle all input and output signals synchronized to the system clock, which is quite amazing, for that is something a short while ago only Static Cache RAM was able to achieve.
The fastest access speed of SDRAM in CPU cycles is 5-1-1-1 for a four data (Byte/Word/Dword) burst read, which makes it exactly as fast as BEDO RAM, however the best thing about SDRAM is that it easily handles bus speeds up to 100 MHz !!!!!!! This is exactly what is needed in the near future, the bus speeds soon will reach these dimensions and only SDRAM seems to be able to keep up with it.
Here some links with more details about SDRAM:
Synchronous DRAMs: The DRAM of the Future http://www.fujitsu-ede.com/sdram/index.html Meeting system demands with Synchronous DRAM technology TI announces production of Synchronous DRAMs
Well, which power user really wants to know about it anymore ? This is the good old cache RAM used for years since the 386 with the first level 2 cache came out. The simple trick of this type of cache RAM is that it's just faster to access than DRAM and depending on your CPU clock you still can get it in 20, 15 or 12 ns flavor, the shorter the access/data time, the faster it is and the shorter the burst access's to it can be chosen. Nevertheless as the name already tells, it's not fast enough to be able to be accessed synchronously, which means that the CPU has to wait on this cache RAM as well, only shorter than it has to wait for DRAM.
Yes, here we are ! Eventually I'm able to clear the long dispute which Burst SRAM is faster, the sync Burst or the Pipelined Burst ? I can hear some wise ones of you say "I knew it !" - yes, with the current bus speeds up to 66 MHz the Sync Burst SRAM is the fastest available ! The reason therefore is that as long as the CPU doesn't run too fast, the Sync Burst SRAM can offer the data indeed synchronously, which means that there's no delay to the CPU 2-1-1-1 burst read - the Sync Burst SRAM delivers the data in 2-1-1-1 burst cycles.
As soon as CPUs do cross the 66 MHz border (as the Cyrix 6x86 P200+ already does) however, the Sync Burst SRAM is overstrain and delivers in 3-2-2-2 bursts, which is significantly slower than Pipelined Burst SRAM.
We can see therefore, that it indeed would make sense to choose Sync Burst SRAM for current Pentium boards, however which M/B does support Sync Burst Cache anymore ? This seems to be down to the fact that less companies produce Sync Burst SRAM and it therefore is more expensive.
You can get Sync Burst SRAM from 8.5 to 12 ns address/data time.
Alright, isn't that the cache RAM we all use already ? And that's what Pipelining means: By employing input or output registers an SRAM may be pipelined. Loading the registers takes an extra lead-off cycle, but once loaded allows early access to the next address location while supplying data from the current location.
Therefore it's the fastest cache RAM for new systems with 75 MHz bus speeds or above. Actually PB SRAM can work with bus speeds up to 133 MHz. Also it's not that much slower than Sync Burst SRAM in slower systems, it delivers in 3-1-1-1 bursts all the way through. You can see how fast it is by its address/data times: 4.5 to 8 ns !
Link about PB SRAM
For a long while 256 kB second level cache was state of the art. Then the Penium P54C came out, and you could install 512 kB cache on your motherboards. The latest VIA Pentium chipsets now support even 2048 kB level 2 cache and everybody is wondering now, if this is making sense.
Up to the time when DOS and Windows 3.1/WfW 3.11 were the mainly used operation systems, there was indeed no point to install more than 256 kB L2 Cache as long as you didn't have more than 64 MB RAM. Since Windows 95 turned up you could see in a lot of benchmarks that a cache size of 512 kB was increasing system performance even with a RAM size of only 16 MB. Now lots of people are thinking of using Windows NT 4.0 others are using OS/2 or UNIX for a long time already, which shows the trend to 32 bit multi tasking operation systems. In 32 bit OSes with multi tasking an increased level 2 cache size up to 2 MB indeed is making sense and will result in increased performance. This is due to the larger size of the actual programs and the larger number of programs which are running at the same time. Hence we see that it's NO overkill to think of getting more than 512 kB L2 cache as long as you're using a modern operation
system.
SRAM Recommendations (by MICRON Technology)
There are several major design implementations with synchronous burst SRAMs that make them far superior to asynchronous SRAMs in high-speed cache design.
1) Synchronized to the system clock: In its simplest form this means that all signals are triggered on a clock edge. The availability of signals on a clock edge simplifies high-speed system design.
2) Burst capability: Synchronous burst SRAMs provide high speed operation by incorporating a small amount of logic that allows the memory to self-cycle through sequential locations. The four-address burst sequence is interleaved for Intel compatibility or linear for PowerPC and others.
3) Pipelining: By employing input or output registers such an SRAM may be pipelined. Loading the registers takes an extra lead-off cycle, but once loaded allows early access to the next address location while supplying data from the current location.
The above features allow the microprocessor access to sequential memory locations faster than the underlying SRAM technology would otherwise support. While some vendors are able to provide 3.3V asynchronous SRAMs with clock-to-data times of 15ns, pipelined synchronous burst SRAMs utilizing a similar technology can achieve clock-to-data times of less than 6ns. The purpose of L2 cache is to enable the microprocessor to run closer to its theoretical limit. Anytime the microprocessor is waiting on instructions or data it is that much further from its performance limit. When discussing SRAM as cache, the most consistent way to compare one solution to another is to compare the number of SRAM access's per cycle during a burst. (All present and future general purpose microprocessors support either interleaved or linear burst schemes.) When
using the burst mode for cache access's the first access takes the microprocessor two cycles.
The second, third and fourth access require only one cycle. Therefore, a zero-wait-state
cache would add no delays to this 2-1-1-1 sequence. As bus frequencies increase,
maintaining a zero-wait-state cache becomes increasingly difficult and prohibitively
expensive for most system design.
This info has been brought to you with the help of Kingston and The RAM.
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